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lp3996 dual linear regulator with 300ma and 150ma outputs and power-on-reset general description the lp3996 is a dual low dropout regulator with power-on- reset circuit. the first regulator can source 150ma, while the second is capable of sourcing 300ma and has a power-on- reset function included. the lp3996 provides 1.5% accuracy requiring an ultra low quiescent current of 35a. separate enable pins allow each output of the lp3996 to be shut down, drawing virtually zero current. the lp3996 is designed to be stable with small footprint ceramic capacitors down to 1f. an external capacitor may be used to set the por delay time as required. the lp3996 is available in fixed output voltages and comes in a 10 pin, 3mm x 3mm, llp package. . features n 2 ldo outputs with independent enable n 1.5% accuracy at room temperature, 3% over temperature n power-on-reset function with adjustable delay n thermal shutdown protection n stable with ceramic capacitors key specifications n input voltage range 2.0v to 6.0v n low dropout voltage 210mv at 300ma n ultra-low i q (enabled) 35a n virtually zero i q (disabled) < 10na package all available in lead free option. 10 pin llp 3mm x 3mm for other package options contact your nsc sales office. applications n cellular handsets n pda?s n wireless network adaptors typical application circuit 20145801 november 2006 lp3996 dual linear regulator with 300ma and 150ma outputs and power-on-reset ? 2006 national semiconductor corporation ds201458 www.national.com
functional block diagram 20145806 pin descriptions llp-10 package pin no symbol name and function 1v in voltage supply input. connect a 1f capacitor between this pin and gnd. 2 en1 enable input to regulator 1. active high input. high = on. low = off. 3 en2 enable input to regulator 2. active high input. high = on. low = off. 4c byp internal voltage reference bypass. connect a 10nf capacitor from this pin to gnd to reduce output noise and improve line transient and psrr. this pin may be left open. 5 set set delay input. connect a capacitor between this pin and gnd to set the por delay time. if left open, there will be no delay. 6 gnd common ground pin. connect externally to exposed pad. 7 n/c no connection. do not connect to any other pin. 8 por power-on reset output. open drain output. active low indicates under-voltage output on regulator 2. a pull-up resistor is required for correct operation. 9v out2 output of regulator 2. 300ma maximum current output. connect a 1f capacitor between this pin and gnd. 10 v out1 output of regulator 1. 150ma maximum current output. connect a 1f capacitor between this pin and gnd. pad gnd common ground. connect to pin 6. lp3996 www.national.com 2
connection diagram llp-10 package 20145803 see ns package number sda10a lp3996 www.national.com 3
ordering information (llp-10) for other voltage options, please contact your local nsc sales office output voltage (v) order number spec package marking supplied as 0.8 / 3.3 lp3996sd-0833 nopb l167b 1000 units, tape-and-reel lp3996sdx-0833 nopb 4500 units, tape-and-reel lp3996sd-0833 1000 units, tape-and-reel lp3996sdx-0833 4500 units, tape-and-reel 1.5 / 2.5 lp3996sd-1525 nopb l168b 1000 units, tape-and-reel lp3996sdx-1525 nopb 4500 units, tape-and-reel lp3996sd-1525 1000 units, tape-and-reel lp3996sdx-1525 4500 units, tape-and-reel 2.8 / 2.8 lp3996sd-2828 nopb l171b 1000 units, tape-and-reel lp3996sdx-2828 nopb 4500 units, tape-and-reel lp3996sd-2828 1000 units, tape-and-reel lp3996sdx-2828 4500 units, tape-and-reel 3.0 / 3.0 lp3996sd-3030 nopb l172b 1000 units, tape-and-reel lp3996sdx-3030 nopb 4500 units, tape-and-reel lp3996sd-3030 1000 units, tape-and-reel lp3996sdx-3030 4500 units, tape-and-reel 3.0 / 3.3 lp3996sd-3033 nopb l170b 1000 units, tape-and-reel lp3996sdx-3033 nopb 4500 units, tape-and-reel lp3996sd-3033 1000 units, tape-and-reel lp3996sdx-3033 4500 units, tape-and-reel 3.3 / 0.8 lp3996sd-3308 nopb l188b 1000 units, tape-and-reel lp3996sdx-3308 nopb 4500 units, tape-and-reel lp3996sd-3308 1000 units, tape-and-reel lp3996sdx-3308 4500 units, tape-and-reel 3.3 / 3.3 lp3996sd-3333 nopb l173b 1000 units, tape-and-reel LP3996SDX-3333 nopb 4500 units, tape-and-reel lp3996sd-3333 1000 units, tape-and-reel LP3996SDX-3333 4500 units, tape-and-reel lp3996 www.national.com 4
absolute maximum ratings (notes 1, 2) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. input voltage to gnd -0.3v to 6.5v v out1 ,v out2 en1 and en2 voltage to gnd -0.3v to (v in + 0.3v) with 6.5v (max) por to gnd -0.3v to 6.5v junction temperature (t j-max ) 150?c lead/pad temp. (note 3) 235?c storage temperature -65?c to 150?c continuous power dissipation internally limited(note 4) esd rating(note 5) human body model 2.0kv machine model 200v operating ratings (notes 1, 2) input voltage 2.0v to 6.0v en1, en2, por voltage 0 to (v in + 0.3v) to 6.0v (max) junction temperature -40?c to 125?c ambient temperature t a range (note 6) -40?c to 85?c thermal properties (note 1) junction to ambient thermal resistance(note 7) ja llp-10 package 55?c/w electrical characteristics (notes 2, 8) unless otherwise noted, v en = 950mv, v in =v out + 1.0v, or 2.0v, whichever is higher, where v out is the higher of v out1 and v out2 .c in = 1 f, i out = 1 ma, c out1 =c out2 = 1.0f. typical values and limits appearing in normal type apply for t a = 25?c. limits appearing in boldface type apply over the full junction temperature range for operation, ?40 to +125?c. symbol parameter conditions typ limit units min max v in input voltage (note 9) 2 6 v ? v out output voltage tolerance i out = 1ma 1.5v < v out 3.3v -2.5 -3.75 +2.5 +3.75 % v out 1.5v -2.75 -4 +2.75 +4 line regulation error v in =(v out(nom) + 1.0v) to 6.0v 0.03 0.3 %/v load regulation error i out = 1ma to 150ma (ldo 1) 85 155 v/ma i out = 1ma to 300ma (ldo 2) 26 85 v do dropout voltage (note 10) i out = 1ma to 150ma (ldo 1) 110 220 mv i out = 1ma to 300ma (ldo 2) 210 550 i q quiescent current ldo 1 on, ldo 2 on i out1 =i out2 = 0ma 35 100 a ldo 1 on, ldo 2 off i out1 = 150ma 45 110 ldo 1 off, ldo 2 on i out2 = 300ma 45 110 ldo 1 on, ldo 2 on i out1 = 150ma, i out2 = 300ma 70 170 v en1 =v en2 = 0.4v 0.5 10 na i sc short circuit current limit ldo 1 420 750 ma ldo 2 550 840 i out maximum output current ldo 1 150 ma ldo 2 300 lp3996 www.national.com 5
electrical characteristics (notes 2, 8) (continued) unless otherwise noted, v en = 950mv, v in =v out + 1.0v, or 2.0v, whichever is higher, where v out is the higher of v out1 and v out2 .c in = 1 f, i out = 1 ma, c out1 =c out2 = 1.0f. typical values and limits appearing in normal type apply for t a = 25?c. limits appearing in boldface type apply over the full junction temperature range for operation, ?40 to +125?c. symbol parameter conditions typ limit units min max psrr power supply rejection ratio (note 11) f = 1khz, i out = 1ma to 150ma c byp = 10nf ldo1 58 db ldo2 70 f = 20khz, i out = 1ma to 150ma c byp = 10nf ldo1 45 ldo2 60 e n output noise voltage (note 11) bw = 10hz to 100khz c byp = 10nf v out = 0.8v 36 v rms v out = 3.3v 75 t shutdown thermal shutdown temperature 160 ?c hysteresis 20 enable control characteristics i en input current at v en1 or v en2 v en = 0.0v 0.005 0.1 a v en =6v 2 5 v il low input threshold at v en1 or v en2 0.4 v v ih high input threshold at v en1 or v en2 0.95 v por output characteristics v th low threshold % 0f v out2 (nom) flag on 88 % high threshold % 0f v out2 (nom) flag off 96 i por leakage current flag off, v por = 6.5v 30 na v ol flag output low voltage i sink = 250a 20 mv timing characteristics t on turn on time (note 11) to 95% level c byp = 10nf 300 s transient response line transient response | v out | (note 11) t rise =t fall = 10s v in = 1vc byp = 10nf 20 mv (pk - pk) load transient response | v out | (note 11) t rise =t fall = 1s ldo 1 i out = 1ma to 150ma 175 ldo 2 i out = 1ma to 300ma 150 set input characteristics i set set pin current source v set = 0v 1.3 a v th(set) set pin threshold voltage por = high 1.25 v lp3996 www.national.com 6
electrical characteristics (notes 2, 8) (continued) note 1: absolute maximum ratings are limits beyond which damage can occur. operating ratings are conditions under which operation of the device is guaranteed. operating ratings do not imply guaranteed performance limits. for guaranteed performance limits and associated test conditions, see t he electrical characteristics tables. note 2: all voltages are with respect to the potential at the gnd pin. note 3: for detailed soldering specifications and information, please refer to national semiconductor application note an-1187, leadless leadframe pack age. note 4: internal thermal shutdown circuitry protects the device from permanent damage. note 5: the human body model is 100pf discharged through a 1.5k ? resistor into each pin. the machine model is a 200pf capacitor discharged directly into each pin. note 6: the maximum ambient temperature (t a(max) ) is dependant on the maximum operating junction temperature (t j(max-op) = 125?c), the maximum power dissipation of the device in the application (p d(max) ), and the junction to ambient thermal resistance of the part/package in the application ( ja ), as given by the following equation: t a(max) =t j(max-op) -( ja xp d(max) ). note 7: junction to ambient thermal resistance is dependant on the application and board layout. in applications where high maximum power dissipation is pos sible, special care must be paid to thermal dissipation issues in board design. note 8: min max limits are guaranteed by design, test or statistical analysis. typical numbers are not guaranteed, but do represent the most likely norm. note 9: v in(min) =v out(nom) + 0.5v, or 2.0v, whichever is higher. note 10: dropout voltage is voltage difference between input and output at which the output voltage drops to 100mv below its nominal value. this parameter only for output voltages above 2.0v note 11: this electrical specification is guaranteed by design. output capacitor, recommended specifications symbol parameter conditions nom limit units min max c out output capacitance capacitance (note 12) 1.0 0.7 f esr 5 500 m ? note 12: the capacitor tolerance should be 30% or better over temperature. the full operating conditions for the application should be considered when select ing a suitable capacitor to ensure that the minimum value of capacitance is always met. recommended capacitor is x7r. however, depending on the applicati on, x5r, y5v and z5u can also be used. (see capacitor section in applications hints). transient test conditions 20145808 figure 1. psrr input signal lp3996 www.national.com 7
transient test conditions (continued) 20145804 figure 2. line transient input test signal 20145805 figure 3. load transient input signal lp3996 www.national.com 8
typical performance characteristics. unless otherwise specified, c in = 1.0f ceramic, c out1 = c out2 = 1.0f ceramic, c byp = 10nf, v in =v out2(nom) + 1.0v, t a = 25?c, v out1(nom) = 3.3v, v out2(nom) = 3.3v, enable pins are tied to v in . output voltage change vs temperature ground current vs load current, ldo1 20145810 20145813 ground current vs load current, ldo2 ground current vs v in .i load = 1ma 20145814 20145815 dropout voltage vs i load , ldo1 dropout voltage vs i load , ldo2 20145811 20145812 lp3996 www.national.com 9
typical performance characteristics. unless otherwise specified, c in = 1.0f ceramic, c out1 = c out2 = 1.0f ceramic, c byp = 10nf, v in =v out2(nom) + 1.0v, t a = 25?c, v out1(nom) = 3.3v, v out2(nom) = 3.3v, enable pins are tied to v in . (continued) short circuit current, ldo1 short circuit current, ldo2 20145852 20145853 power supply rejection ratio, ldo1 power supply rejection ratio, ldo2 20145855 20145854 enable start-up time, c byp =0 enable start-up time, c byp =10nf 20145860 20145861 lp3996 www.national.com 10
typical performance characteristics. unless otherwise specified, c in = 1.0f ceramic, c out1 = c out2 = 1.0f ceramic, c byp = 10nf, v in =v out2(nom) + 1.0v, t a = 25?c, v out1(nom) = 3.3v, v out2(nom) = 3.3v, enable pins are tied to v in . (continued) line transient, c byp =10nf line transient, c byp =0 20145819 20145820 load transient, ldo1 load transient, ldo2 20145850 20145851 noise density ldo1 noise density, ldo2 20145856 20145857 lp3996 www.national.com 11
typical performance characteristics. unless otherwise specified, c in = 1.0f ceramic, c out1 = c out2 = 1.0f ceramic, c byp = 10nf, v in =v out2(nom) + 1.0v, t a = 25?c, v out1(nom) = 3.3v, v out2(nom) = 3.3v, enable pins are tied to v in . (continued) power-on-reset start-up operation power-on-reset shutdown operation 20145816 20145817 por delay time 20145818 lp3996 www.national.com 12
application hints operation description the lp3996 is a low quiescent current, power management ic, designed specifically for portable applications requiring minimum board space and smallest components. the lp3996 contains two independently selectable ldos. the first is capable of sourcing 150ma at outputs between 0.8v and 3.3v. the second can source 300ma at an output volt- age of 0.8v to 3.3v. in addition, ldo2 contains power good flag circuit, which monitors the output voltage and indicates when it is within 8% of its nominal value. the flag will also act as a power-on-reset signal and, by adding an external ca- pacitor; a delay may be programmed for the por output. input capacitor an input capacitor is required for stability. it is recommended that a 1.0f capacitor be connected between the lp3996 input pin and ground (this capacitance value may be in- creased without limit). this capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analogue ground. any good quality ceramic, tantalum, or film capacitor may be used at the input. important: tantalum capacitors can suffer catastrophic fail- ures due to surge current when connected to a low- impedance source of power (like a battery or a very large capacitor). if a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. there are no requirements for the esr (equivalent series resistance) on the input capacitor, but tolerance and tem- perature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain approxi- mately 1.0f over the entire operating temperature range. output capacitor the lp3996 is designed specifically to work with very small ceramic output capacitors. a 1.0f ceramic capacitor (tem- perature types z5u, y5v or x7r) with esr between 5m ? to 500m ? , is suitable in the lp3996 application circuit. for this device the output capacitor should be connected between the v out pin and ground. it is also possible to use tantalum or film capacitors at the device output, c out (or v out ), but these are not as attrac- tive for reasons of size and cost (see the section capacitor characteristics). the output capacitor must meet the requirement for the minimum value of capacitance and also have an esr value that is within the range 5m ? to 500m ? for stability. no-load stability the lp3996 will remain stable and in regulation with no external load. this is an important consideration in some circuits, for example cmos ram keep-alive applications. capacitor characteristics the lp3996 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. for capacitance values in the range of 0.47f to 4.7f, ceramic capacitors are the smallest, least expensive and have the lowest esr values, thus making them best for eliminating high frequency noise. the esr of a typical 1.0f ceramic capacitor is in the range of 20m ? to 40m ? , which easily meets the esr requirement for stability for the lp3996. for both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct de- vice operation. the capacitor value can change greatly, de- pending on the operating conditions and capacitor type. in particular, the output capacitor selection should take ac- count of all the capacitor parameters, to ensure that the specification is met within the application. the capacitance can vary with dc bias conditions as well as temperature and frequency of operation. capacitor values will also show some decrease over time due to aging. the capacitor pa- rameters are also dependant on the particular case size, with smaller sizes giving poorer performance figures in gen- eral. as an example, figure 4 shows a typical graph com- paring different capacitor case sizes in a capacitance vs. dc bias plot. as shown in the graph, increasing the dc bias condition can result in the capacitance value falling below the minimum value given in the recommended capacitor specifications table (0.7f in this case). note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. it is therefore recom- mended that the capacitor manufacturers? specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual application. the ceramic capacitor?s capacitance can vary with tempera- ture. the capacitor type x7r, which operates over a tem- perature range of -55?c to +125?c, will only vary the capaci- tance to within 15%. the capacitor type x5r has a similar tolerance over a reduced temperature range of -55?c to +85?c. many large value ceramic capacitors, larger than 1f are manufactured with z5u or y5v temperature characteris- tics. their capacitance can drop by more than 50% as the temperature varies from 25?c to 85?c. therefore x7r is recommended over z5u and y5v in applications where the ambient temperature will change significantly above or be- low 25?c. tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47f to 4.7f range. 20145840 figure 4. graph showing a typical variation in capacitance vs dc bias lp3996 www.national.com 13
application hints (continued) another important consideration is that tantalum capacitors have higher esr values than equivalent size ceramics. this means that while it may be possible to find a tantalum capacitor with an esr value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same esr value. it should also be noted that the esr of a typical tantalum will increase about 2:1 as the temperature goes from 25?c down to -40?c, so some guard band must be allowed. enable control the lp3996 features active high enable pins for each regu- lator, en1 and en2, which turns the corresponding ldo off when pulled low. the device outputs are enabled when the enable lines are set to high. when not enabled the regulator output is off and the device typically consumes 2na. if the application does not require the enable switching feature, one or both enable pins should be tied to v in to keep the regulator output permanently on. to ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and below the specified turn-on / off voltage thresholds listed in the electri- cal characteristics section under v il and v ih . power-on-reset the por pin is an open-drain output which will be set to low whenever the output of ldo2 falls out of regulation to ap- proximately 90% of its nominal value. an external pull-up resistor, connected to v out or v in , is required on this pin. during start-up, or whenever a fault condition is removed, the por flag will return to the high state after the output reaches approximately 96% of its nominal value. by con- necting a capacitor from the set pin to gnd, a delay to the rising condition of the por flag may be introduced. the delayed signal may then be used as a power-on -reset for a microprocessor within the user?s application. the duration of the delay is determined by the time to charge the delay capacitor to a threshold voltage of 1.25v at 1.2a from the set pin as in the formula below. 20145841 a 0.1f capacitor will introduce a delay of approximately 100ms. bypass capacitor the internal voltage reference circuit of the lp3996 is con- nected to the c byp pin via a high value internal resistor. an external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on both outputs of the device. there is also some improvement in pssr and line transient performance. internal circuitry ensures rapid charg- ing of the c byp capacitor during start-up. a 10nf, high quality ceramic capacitor with either npo or cog dielectric is rec- ommended due to their low leakage characteristics and low noise performance. safe area of operation due consideration should be given to operating conditions to avoid excessive thermal dissipation of the lp3996 or trigger- ing its thermal shutdown circuit. when both outputs are enabled, the total power dissipation will be p d(ldo1) +p d(ldo2) where p d =(v in -v out )xi out for each ldo. in general, device options which have a large difference in output voltage will dissipate more power when both outputs are enabled, due to the input voltage required for the higher output voltage ldo. in such cases, especially at elevated ambient temperature, it may not be possible to operate both outputs at maximum current at the same time. lp3996 www.national.com 14
physical dimensions inches (millimeters) unless otherwise noted llp, 10 lead, package ns package number sda10a lp3996 www.national.com 15
the contents of this document are provided in connection with national semiconductor corporation ( national ) products. national makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. testing and other quality controls are used to the extent national deems necessary to support national?s product warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. national assumes no liability for applications assistance or buyer product design. buyers are responsible for their products and applications using national components. prior to using or distributing any products that include national components, buyers should provide adequate design, testing and operating safeguards. except as provided in national?s terms and conditions of sale for such products, national assumes no liability whatsoever, and national disclaims any express or implied warranty relating to the sale and/or use of national products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. life support policy national?s products are not authorized for use as critical components in life support devices or systems without the express prior written approval of the chief executive officer and general counsel of national semiconductor corporation. as used herein: life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. a critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. national semiconductor and the national semiconductor logo are trademarks or registered trademarks of national semiconductor corporation. all other brand or product names may be trademarks or registered trademarks of their respective holders. copyright ? 2006 national semiconductor corporation. for the most current product information visit us at www.national.com. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com lp3996 dual linear regulator with 300ma and 150ma outputs and power-on-reset

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